Photolithography is commonly used to make miniaturized electronic components such as integrated circuits in semiconductor manufacturing. In a photolithography process, a layer of photoresist is deposited on a substrate, such as a silicon wafer. The substrate is baked to remove any solvent remained in the photoresist layer. The photoresist is then selectively exposed through a photomask with a desired pattern to a source of actinic radiation. The radiation exposure causes a chemical reaction in the exposed areas of the photoresist and creates a latent image corresponding to the mask pattern in the photoresist layer. The photoresist is next developed in a developer solution to remove either the exposed portions of the photoresist for a positive photoresist or the unexposed portions of the photoresist for a negative photoresist. The patterned photoresist can then be used as a mask for subsequent fabrication processes on the substrate, such as deposition, etching, or ion implantation processes.
Advances in semiconductor device performance have typically been accomplished through a decrease in semiconductor device dimensions. It is known that the tip-to-tip spacing between lines (e.g., PC lines) has a high impact on the unit cell density of the semiconductor device. Reducing the tip-to-tip distance between lines will greatly increase the unit cell density which in turn will lead to a shrinkage in the device dimension. However, due to the line end shortening issue and the resolution limitation of photolithography, the currently available lithographic techniques can only achieve a tip-to-tip distance of not less than 100 nm.
It has been known that certain materials are capable of organizing into ordered structures without the need for human interference, which is referred to as the self-assembly of materials. Self-assembling copolymer lithographic techniques have been developed to form useful periodic patterns with dimensions in the range of 10 to 40 nm. Each self-assembling block copolymer system contains two or more different polymeric block components which are immiscible with one another. Under suitable conditions, these polymeric block components can separate into two or more different phases on a nanometer-scale and thereby form ordered nano-sized patterns. Such ordered patterns can be used for fabricating nano-scale structural units in semiconductor, optical and magnetic devices.
However, the complementary metal oxide semiconductor (CMOS) technology requires precise placement or registration of individual structural units to form metal lines and vias in the wiring level. The large, ordered array of repeating structural units formed by self-assembling block copolymers cannot be used in the CMOS technology, because of the lack of alignment or registration of the positions of individual structural units.